close
library ieee;
use IEEE.STD_LOGIC_1164.all;
entity table is
port (X:in STD_LOGIC_VECTOR(3 downto 0);
Y:out STD_LOGIC);
end table;
architecture a of table is
begin
Y <= '1' when X="0010" else
'1' when X="0011" else
'1' when X="0101" else
'1' when X="0111" else
'0';
end a;
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